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Features
* * * * * * * * * *
Low Current Consumption: IVDD < 25 A RC Oscillator Internal Reset During Power-up and Supply Voltage Drops (POR) "Short" Trigger Window for Active Mode "Long" Trigger Window for Sleep Mode Cyclical Wake-up of the Microcontroller in Sleep Mode Trigger Input Single Wake-up Input Reset Output Enable Output
Digital Window Watchdog Timer ATA5021
1. Description
The digital window watchdog timer, ATA5021, is designed in Atmel(R)'s state-of-the-art 0.8 m SOI technology SMART-I.S.TM1. In applications where safety is critical, it is especially important to monitor the microcontroller. Normal microcontroller operation is indicated by a cyclically transmitted trigger signal, which is received by a window watchdog timer within a defined time window. A missing or a wrong trigger signal causes the watchdog timer to reset the microcontroller. The IC is tailored for microcontrollers, which can work in both full-power and sleep mode. With an additional voltage monitoring (power-on reset and supply voltage drop reset), the ATA5021 offers a complete monitoring solution for micro-systems in automotive and industrial applications.
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Figure 1-1.
Block Diagram with External Circuit
C VDD 10 nF R1 6 OSC 8 C1 Reset 5 RC oscillator OSC
VDD
Microcontroller Trigger 2
State machine OSC Input signal conditioning POR Power-on reset POR Test logic 4 Enable External switching circuitry
Mode 3
Wake-up
1 GND
7
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2. Pin Configuration
Figure 2-1. Pinning SO8
WUP TRIG MODE ENA
1 2 3 4 8 7 6 5
OSC GND VDD RESET
Table 2-1.
Pin 1
Pin Description
Symbol WUP Function Wake-up input (pull-down resistor) There is one digitally debounced wake-up input. During the long watchdog window, each signal slope at the input initiates a reset pulse at pin 5. Trigger input (pull-up resistor) It is connected to the microprocessor's trigger signal. Mode input (pull-up resistor) The processor's mode signal initiates the switchover between the long and the short watchdog time. Enable output (push-pull) It is used for the control of peripheral components. It is activated after the processor triggers three times correctly. Reset output (open drain) Resets the processor in the case of under-voltage condition, a wrong trigger event or if a wake-up event occurs during long watchdog period. Supply voltage Ground, reference voltage RC oscillator
2 3
TRG MODE
4
ENA
5 6 7 8
RESET VDD GND OSC
3
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3. Functional Description
3.1 Supply Voltage, Pin 6
The ATA5021 requires a stabilized supply voltage VDD = 5V 10% to comply with its electrical characteristics. An external buffer capacitor of C = 10 nF may be connected between pin 6 and GND.
3.2
RC Oscillator, Pin 8
The clock frequency, f, can be adjusted by the components R1 and C1 according to the formula: 1 f = -- with T T = 0.18 x (C1 + Cboard + 0.016) + 0.35 + [1.59 - (C1 + Cboard + 0.016)/85] x R1 x (C1 + Cboard + 0.016) R1 (k) = external resistor at pin 8 C1 (nF) = external capacitor at pin 8 Cboard = 0.004 nF; this is the parasitic test board capacity caused by additional wiring on the test assembly. With frequency calculations of original boards, this parasitic capacitor can be omitted.
Table 3-1.
Comparison Table Clock Period Calculation versus Measurement on Test Board
Period "T" (s) by New Formula 4.36 8.20 17.26 74.40 156.30 13.45 25.99 55.57 242.10 509.25 18.92 36.69 78.63 343.03 721.70 27.38 53.22 114.25 498.94 1049.85 32.61 Period "T" (s) by Measurement 4.33 8.30 17.10 74.50 152.00 13.25 26.13 55.00 241.50 505.00 18.50 36.63 78.25 341.25 700.00 26.75 53.25 112.50 497.50 1020.00 31.88 Deviation of New Formula versus Measurement -0.3% 1.8% 1.4% 1.5% -2.2% -0.4% 1.9% 1.2% 1.2% 1.6% -1.2% 0.8% 1.7% 0.6% -1.6% -1.4% 1.4% 1.5% 1.2% 0.0% -1.1%
R1 (k) 10.00 10.00 10.00 10.00 10.00 32.91 32.91 32.91 32.91 32.91 46.70 46.70 46.70 46.70 46.70 68.00 68.00 68.00 68.00 68.00 81.20
C1 (nF) 0.23 0.47 1.04 4.75 10.49 0.23 0.47 1.04 4.75 10.49 0.23 0.47 1.04 4.75 10.49 0.23 0.47 1.04 4.75 10.49 0.23
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Table 3-1. Comparison Table Clock Period Calculation versus Measurement on Test Board
Period "T" (s) by New Formula 63.47 136.32 595.56 1253.21 40.07 78.07 167.76 733.17 1542.84 47.81 93.20 200.37 875.90 1843.26 Period "T" (s) by Measurement 63.75 135.00 592.50 1240.00 38.88 78.00 164.00 730.00 1530.00 46.38 93.00 200.25 870.00 1835.00 Deviation of New Formula versus Measurement 1.6% 1.9% 0.7% 1.3% -2.1% 1.2% -1.7% 0.9% 0.5% -1.7% 0.8% 1.1% 0.5% 0.9%
R1 (k) 81.20 81.20 81.20 81.20 100.00 100.00 100.00 100.00 100.00 119.50 119.50 119.50 119.50 119.50
C1 (nF) 0.47 1.04 4.75 10.49 0.23 0.47 1.04 4.75 10.49 0.23 0.47 1.04 4.75 10.49
The clock frequency determines all time periods of the logical part as shown in Section 7. "Electrical Characteristics" on page 9 under the subheading "Timing".
3.3
Supply Voltage Monitoring, Pin 5
During ramp-up of the supply voltage and in the case of supply-voltage drops, the integrated power-on reset (POR) circuitry sets the internal logic to a defined basic status and generates a reset pulse at the reset output, pin 5. A hysteresis in the POR threshold prevents the circuit from oscillating. During ramp-up of the supply voltage, the reset output stays active for a specified period of time (t0) in order to bring the microcontroller into its defined reset status (see Figure 3-1 on page 5).
3.4
Switch-over Mode Time, Pin 3
The switch-over mode time enables the synchronous operation of microcontroller and watchdog. When the power-on reset time has elapsed, the watchdog has to be switched to monitoring mode by the microcontroller by a "low" signal transmitted to the mode pin (pin 3) within the time-out period, t1. If the low signal does not occur within t1 (see Figure 3-1 on page 5), the watchdog generates a reset pulse, t6, and t1 starts again. Microcontroller and watchdog are synchronized with the switch-over mode time, t1, each time a reset pulse is generated.
Figure 3-1.
Power-on Reset and Switch-over Mode
VDD t0 Reset out t6 Pin 5 Pin 6
t1
Mode
Pin 3
5
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3.5
3.5.1
Microcontroller in Active Mode
Monitoring with the "Short" Trigger Window After the switch-over mode, the watchdog operates in short watchdog mode and expects a trigger pulse from the microcontroller within the defined time window, t 3 , (enable time). The watchdog generates a reset pulse which resets the microcontroller if: * the trigger pulse duration is too long * the trigger pulse is within the disable time, t2 * there is no trigger pulse Figure 3-2 shows the pulse diagram with a missing trigger pulse.
Figure 3-2.
Pulse Diagram with no Trigger Pulse during the Short Watchdog Time
VDD t0 Reset out t2 Mode t3 Pin 3 t1 Pin 5 Pin 6
Trigger
Pin 2
Figure 3-3 shows a correct trigger sequence. The positive edge of the trigger signal starts a new monitoring cycle with the disable time, t2. To ensure correct operation of the microcontroller, the watchdog needs to be triggered three times correctly before it sets its enable output. This feature is used to activate or deactivate safety-critical components, which have to be switched to a certain condition (emergency status) in the case of a microcontroller malfunction. As soon as there is an incorrect trigger sequence, the enable signal is reset and it takes a sequence of three correct triggers before enable is active. For proper operation, the trigger pulse duration must be longer than the input signal debounce time (see item 4.2 in Section 7. "Electrical Characteristics" on page 9) and must not exceed the maximum duration of 45 clock cycles (see item 4.4 in Section 7. "Electrical Characteristics" on page 9). Figure 3-3. Pulse Diagram of a Correct Trigger Sequence during the Short Watchdog Time
VDD t0 Reset out t2 Mode t1 Pin 5 t2 Pin 3 Pin 6
t3
Trigger ttrig Enable
Pin 2
Pin 4
6
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3.6
3.6.1
Microcontroller in Sleep Mode
Monitoring with the "Long" Trigger Window The long watchdog mode allows cyclical wake-up of the microcontroller during sleep mode. As in short watchdog mode, there is a disable time, t4, and an enable time, t5, in which a trigger signal is accepted. The watchdog can be switched from the short trigger window to the long trigger window with a "high" potential at the mode pin (pin 3). In contrast to the short watchdog mode, the time periods are now much longer and the enable output remains inactive so that other components can be switched off to effect a further decrease in current consumption. As soon as a wake-up signal at the wake-up input (pins 1) is detected, the long watchdog mode ends, a reset pulse wakes-up the sleeping microcontroller and the normal monitoring cycle starts with the mode switch-over time. Figure 3-4 shows the switch-over from the short to the long watchdog mode. The wake-up signal during the enable time, t5, activates a reset pulse, t6. The watchdog can be switched back from the long to the short watchdog mode with a low potential at the mode pin (pin 3).
Figure 3-4.
Pulse Diagram of the Long Watchdog Time
t6 Reset out Pin 5 Wake-up t4 Mode t2 Trigger Pin 2 t5 Pin 3 Pin 1 t1
Enable
Pin 4
3.7
Reset-Out, Pin 5
The Reset-out pin functionality is guaranteed for supply voltage down to 1V. In case of a voltage drop, the microcontroller gets a reset up to that value.
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4. State Diagram
The kernel of the watchdog is a finite state machine. Figure 4-1 shows the state diagram with all possible states and transmissions. Many transmissions are controlled by an internal timer. The numbers for the time-outs are the same as on the pulse diagrams. Figure 4-1. State Diagram of the Finite State Machine
Reset State
time-out t0
mode_d = 0
mode_d = 1
Mode Switch State
Short Window Disable State
mode_d = 0
Long Window Disable State
mode_d = 1 time-out t1 trg_ok trg_d = 0 mode_d = 0 time-out t2 time-out t4 trg_ok
time-out t6
time-out t3 OR trg_err
Short Window Enable State
time-out t5 OR trg_err OR wedge
Long Window Disable State
Reset Out State
trg_d = 0 OR wedge
Notes: 1. mode_d and trg_d are the debounced signals of the MODE and TRG pins 2. wedge is the detection of a signal edge on the wake-up pin after the deboucing time 3. trg_ok is valid for once cycle after the rising edge on trg_d 4. trg_err is valid if the low period of trg_d is too long
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5. Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Voltage range on pin VDD Voltage range on pins Output current HBM ESD ANSI/ESD-STM5.1 JESD22-A114 AEC-Q100 (002) Ambient temperature range Storage temperature range Pin Symbol VVDD,max VIO,max IOUT,max VESD,HBM Tamb Tsto Min. -0.4 -0.4 -2 Max. +6.5 VVDD + 0.4 +2 Unit V V mA
2
kV
-40 -55
+125 +150
C C
6. Thermal Resistance
Parameters Thermal case resistance junction ambient Symbol RthJA Value 180 Unit K/W
7. Electrical Characteristics
VVDD = 5V, Tamb = -40C to +125C, reference point is pin 7, unless otherwise specified. No. Parameters Test Conditions VVDD = 5V R1 = 66 k C1 = 470 pF Release reset state with rising supply voltage Get reset state with falling supply voltage VVDD = 1V to VPOR1 IRTO = 300 A VVDD = 5V VVDD = 5V VVDD = 5V VIN = 5V VVDD = 5V VIN = 0V VVDD = 5V Pin Symbol Min. Typ. Max. Unit Type* Power Supply 1.1 Current Consumption 6 IVDD VPOR1 VPOR2 VPOR,hys VRST 3.9 3.8 40 25 A A
1.2 Power-on-reset 1.3 1.4 1.5 Inputs 2.1 2.2 2.3 2.4 2.5 Logical "high" Logical "low" Hysteresis Pull-down current Pull-up current POR hysteresis Reset Level for low VDD
6 6 6 5
4.5 4.4 200 0.1
V V mV VVDD
A A A A
1, 2, 3 1, 2, 3 1, 2, 3 1 2, 3
VIH VIL VIN_hys IPD IPU
3.4 1.6 0.6 5 -20 1 1.4 20 -5
V V V A A
A A A A A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Frequency deviation also depends on the tolerances of the external components 2. Cycle = Period of clock frequency (see Section 3.2 on page 4)
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7. Electrical Characteristics (Continued)
VVDD = 5V, Tamb = -40C to +125C, reference point is pin 7, unless otherwise specified. No. Outputs 3.1 3.2 3.3 3.4 Timing 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 Notes: R1 = 66 k Frequency deviation (1) C1 = 470 pF VVDD = 4.5V to 5V(2) Debounce time Maximum trigger pulse length Power-up reset time Switch-over mode time Disable time Enable time Disable time Enable time Reset-out time Short watchdog window Short watchdog window Long watchdog window Long watchdog window 8 2,3 1 3 fdev tdeb1 tdeb2 ttrgmax t0 t1 t2 t3 t4 t5 t6 3 96 45 201 1112 130 124 71970 30002 40 5 4 128 % Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle C D D D D D D D D D D Maximum output current Logical output "low" Logical output "high" Leakage current IOUT = 1 mA IOUT = -1 mA VOUT = 5V 4, 5 4, 5 4 5 IOUT VOL VOH Ileak VVDD - 0.2 2 -2 +2 0.2 mA V V A C A A A Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 1. Frequency deviation also depends on the tolerances of the external components 2. Cycle = Period of clock frequency (see Section 3.2 on page 4)
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8. Ordering Information
Extended Type Number ATA5021-TAPY ATA5021-TAQY Package SO8 SO8 Remarks Taped and reeled, Pb-free, small reel Taped and reeled, Pb-free, big reel
9. Package Information
Package: SO 8 Dimensions in mm 4.90.1 50.2 3.70.1
0.2
0.1+0.15
1.4
0.4 1.27 3.81
3.80.1 60.2
8
5
technical drawings according to DIN specifications
1 Drawing-No.: 6.541-5031.01-4 Issue: 1; 15.08.06
4
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10. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 9145D-AUTO-05/10 9145C-AUTO-09/09 History * Section 3.2 "RC Oscillator, Pin 8" on pages 4 to 5 changed * Section 3.2 "RC Oscillator, Pin 8" on page 4 changed * El. Char. Table: rows 3.1, 3.2, 3.3 changed * * * * Put datasheet in the newest template Section 3.2 ""RC Oscillator, Pin 8" on pages 4 to 6 updated Section 3.5 "Microcontroller in Active Mode" on page 7 updated Section 7 "Electrical Characteristics" numbers 1.1 and 4.1 on pages 10 to 11 updated
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